GATE EE 2012 Digital Electronics Q 4 - Grad Plus
GATE EE 2012 Digital Electronics Q 4

GATE EE 2012 Digital Electronics Q 4

The state transition diagram for the logic circuit shown is

Ans: (d)

Explanation

When A=1, then outp put Q will be selected by MUX and feedback to D flipflop which gives output Q again. So at A=1 it holds its state.

But, when A=0, then \overline Q will be selected by MUX and feedback to D flipflop and output will be inverted. And after every clock pulse output will be toggled due to section of \overline Q.

So option (d) is correct option.

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