GATE EE 2013 Digital Electronics Q 3 - Grad Plus
GATE EE 2013 Digital Electronics Q 3

GATE EE 2013 Digital Electronics Q 3

In the circuit shown below, Q1 has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If Vcc is +5 V, X and Y are digital signals with 0 V as logic 0 and Vcc as logic 1, the Boolean expression for Z is

(a) XY

(b) \overline XY

(c) X\overline Y

(d) \overline X\overline Y

Ans: (b)

Explanation

XYQZ
00OFF0
0+5VOFF+5V
+5V0ON0
+5V+5VON0

Solving for Z, we get Z=\overline XY

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