GATE EE 2014 Digital Electronics Q 6 - Grad Plus
GATE EE 2014 Digital Electronics Q 6

GATE EE 2014 Digital Electronics Q 6

A state diagram of a logic which exhibits a delay in the output is shown in the figure, where X is the do not care condition, and Q is the output representing the state.

The logic gate represented by the state diagram is

a) XOR

b) OR

c) AND

d) NAND

Ans: (d)

Explanation

ABQ
001
011
101
110

This represents the NAND gate.

Scroll to Top