GATE EE 2015 Digital Electronics Q 5 - Grad Plus
GATE EE 2015 Digital Electronics Q 5

GATE EE 2015 Digital Electronics Q 5

The figure shows a digital circuit constructed using negative edge triggered J-K flip flops. Assume a starting state of Q2Q1Q0=000 will repeat after ______ number of cycles of the clock CLK

Ans: 6

Explanation

From the circuit, JK Flip-flop 1 and 2 form a synchronous sequential circuits and they are synchronized with the output of 0th JK Flip-flop.

Number of cycles=3 i.e. equal to 6 clock cycles.

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