GATE EE 2017 Digital Electronics Q 4 - Grad Plus
GATE EE 2017 Digital Electronics Q 4

GATE EE 2017 Digital Electronics Q 4

For the synchronous sequential circuit shown below, the output Z is zero for the initial conditions Q_AQ_BQ_C=Q_{A}^{'}\;Q_{B}^{'}\;Q_{C}^{'}=100

The minimum number of clock cycles after which the output Z would again become zero is ____.

Ans: 6

Explanation

ClockQAQBQCαAαBαCQ_A\oplus\alpha_AQ_B\oplus\alpha_BQ_C\oplus\alpha_CZ
0
1
2
3
4
5
6
1
0
0
1
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
1
0
1
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
1
1
1
1
1
0

The output Z will again become zero after 6 clock cycles.

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