Q 7a) Draw and Explain Maximum mode of 8086 Microprocessor [07 M]
Ans :
In the maximum mode, the 8086 is operated by strapping MN/MC pin to ground.
– In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller derives the control signal using status information.
-In maximum mode, there may be more than one micro processor in the system configuration.
-The components in the system are same as minimum mode system.
-The basic function of bus controller chip IC 8288 is to derive control signals likes RD & WR (for memory & I/O devices) DEN, DT/R, ALE using the information by the processor on status lines.
– Bus controller Chip has input lines s2, s1, s0 & clk these inputs to 8288 are driven by CPU.
– It derives the output ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC, AIOWC. The ALE, IOB, CEN, Pine are specially useful for multiprocessor system.
– AEN & IOB are generally grounded CEN pin is usually tied to +5V. The significance of MCE /PDEN output depend upon the status of IOB pin.
-If IOB is grounded, it acts as master cascade enable to control cascade 8259 A, else it acts as peripheral data enable used in the multiple bus configuration.
-INTA pin used to issue two interrupt acknowledge pulse to interrupt controller or to an interrupting device.
-IORC/IOWC are I/O read command & I/O write command signals.
-MRDC, MWTC are memory read command & memory write command signals & may be used as read or write of memory signals.
– All these command signals instruct the for memory to accepts or send data from or to the bus.
-For both of these write command signals, the advanced signal namely AIWOC & AMNTC are available.
-P0, S1, S2 are set at the beginning of bus cycle 8288 bus controller will output a pulses as an the ALE & apply a required signal to its PT/R pin during T1 .
-If reader input is not active before T3 wait state will be inserted between T3 & T4.
Q 7 b) Draw & Explain architecture of 8237 DMA. [06 M]
Ans :
8237 DMA internal block diagram consist of :
-Control Register
-Internal Register
8237 contain three basic block of control logic :
(1) Timing & Control Block :
It generates internal timing and external control signal to 8237.
(2) Program Command Control Block :
It decodes various command given to 8237 by the microprocessor before servicing a DMA request. It also decodes the mode control word, which is used to select the type of DMA during the servicing.
(3) Internal Registers :
8237 Contain 344 bits of internal memory in the form of Registers.
CAR :
-The Current Address Register holds a 16 bits memory address used for DMA transfer .
-Each channels has its own current address register for this purpose.
-When a byte of data is transferred during a DMA operation, CDP is either incremented or decremented depending on how it is programmed.
CWCR :
-The Current Word court Register program a channel for the number of bytes to transformed during a DMA action.
CR :
-The command Register program the operation of 8237 DMA Controller.
-The Register uses bit position 0 to select the memory DMA transfer mode.
(1) Memory to Memory DMA transfer use DMA channel.
(2) DMA channel 0 to hold the source address.
(3) DMA channel 1 hold the distribution channels.
BA & BWC :
-The base address and base word count register are used when auto-initialization is selected for a channel.
-In auto initialization mode, these register are used to reload the CAR & CWCR after the DMA action is completed.
MR :
-Mode Register Programs the mode of operations for a channel.
-Each channel has its own mode Register selected by bit position 1 & 0 .
BR :
-The bus required Register is used to request a DMA via. Software.
MRSR :
The mark register set / reset set or clears the channel mask.
– If the mask is set, channel is disabled.
-The RESET signals set all this channel mask to disable them.
MSR :
The mask register clears or set all the masks with one command instead of individual channels, as with the MRSR.
SR :
The status Register shows status of each DMA channel. The TC Bits indicate if the channel has reached its terminal count.
-When the terminal count is reached, the DMA transfer is terminated for most modes of operation.