Digital System Design-Engineering-Mumbai University-Dec2019 - Grad Plus

# Digital System Design-Engineering-Mumbai University-Dec2019

## Semester: 3

[Total Time: 3 Hours]
[Total Marks: 80 M]
N.B.
1. Question No. 1 is compulsory.
2. Out of remaining questions, attempt any three questions.
3. Assume suitable additional data if required.
4. Figures in brackets on the right hand side indicate full marks.

Q.1 (A) The Gray code for decimal number 6 is equivalent to (01M)
i) 0100 ii) 0001
iii) 0101 iv) 0110 Prove it.  (04M)

(B) Which of the following is correct statement: (01M)
i) PLA contains a fixed AND array and a programmable OR array.
ii) PLA contains a programmable AND array and a programmable OR array.
iii) PAL contains a fixed AND array and a programmable OR array.
iv) PAL contains a programmable AND array and a programmable OR array.
Draw the structure of correct statement. (04M)

(C) Which of the following expression is equivalent to Z – A B + C where A represents MSB and C represents LSB of the binary numbers? (01M)
i) Z -∑ m (0 , 2 , 6 ).  ii) Z -Π  M (1, 3, 4 , 5, 7 ).
iii) Z -∑  m (1, 3, 4 , 5 , 7 ) + d ( 6 ).  iv) Z – Π M (0 , 2 , 6 ).
Prove it. (04M)

(D) A single 4-bit magnitude comparator IC 7485 can compare maximum (01M)
i) two 4-bit numbers ii) two 5-bit numbers
iii) two 8-bit numbers iv) two 10-bit numbers
Draw its corresponding diagram (04M)

Q.2 (A) Implement the following Boolean equation using single 4:1 MUX and few logic
gates: F ( A , B , C , D ) – ∑ m (0 , 2 , 5 , 6 , 7 , 9 , 12 , 15 ). (10M)

(B) Write the VHDL code for Fibonacci Series Generator sequential circuit. (10M)

Q.3 (A) Design synchronous counter using D type flip flops for getting the following sequence: 0 →2 →4 →6→ 0. Take care of lockout condition. (10M)

(B) Compare SRAM with DRAM. (05M)

(C) What are the Universal Gates? Why are they so called? Design any one Basic Logic Gate using only Universal Gates. (05M)

Q.4 (A) Draw a neat circuit of BCD adder using IC 7483 and explain. (10M)

(B) Using Quine Mc’Clusky method, minimize the following: (10M)
F ( A , B , C ,.D ) – ∑ m (0 , 3, 5 , 7 , 8, 11 , 13 , 15 ).

Q.5 (A) With neat diagram, explain the working of Universal Shift Registers. Give its applications. (10M)

(B) Analyze the circuit given in Figure 5(B). Assume initial state as A=0, B=0. Complete a state table that shows the behavior of this state machine. Is this a Moore or Mealy machine? (Explain with a sentence) (10M)

6. (A) Convert T type flip flop into D type flip flop. (05M)

(B) Compare Moore with Mealy circuits. (05M)

(C) Compare PAL with PLA. (05M)

(D) Compare FPGA with CPLD. (05M)

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