May 2019 Solutions Q1
Q 1 a) Design 3 bit binary to grey code converter
Ans :
G0 = \overline{B_1} B0 + B1 \overline {B_0}
= B0 ⊕ B1
G1 :
G1 = B2 \overline{B_1} + \overline{B_2} B1
= B1 ⊕ B2
G2 :
G2 = B2
Logic Diagram :
Q 1 b) Convert D F/F to J/K F/F
Ans :
Available FF = D FF
Required FF = JK FF
Step1 : write characteristics table of required FF
| Qn | J | K | Qn+1 |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |
Step 2 : Write excitation table of available FF
| Qn | Qn+1 | D |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Step3 : complete the table in step1 by writing D inputs using excitation table
| Qn | J | K | Qn+1 | D |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 0 |
| 0 | 1 | 0 | 1 | 1 |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 0 |
Step 4 : solve for D in terms of J,K and Qn
D = Qn \overline{K} + \overline{Q_n} J
Circuit diagram :
