LinkedIn Insight BSc.-Digital Electronics-Mumbai-November 2017 - Grad Plus

BSc.-Digital Electronics-Mumbai-November 2017

MUMBAI UNIVERSITY

Digital electronics

Q.P. Code :00898

Sem : 1

[Time: 2 Hours
[Marks: 75
Please check whether you have got the right question paper.
NB 1 All questions are compulsory.
2 Make suitable assumptions wherever necessary and state the assumption mode.
3 Answer to the same question must be written together.
4 Numbers to the right indicate marks.
5 Draw at labeled dugem whenever necessary.
6 Use a Non-proteammabig calculator is allowed.

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Q. 1 Attempt any three of the following. (15M)

a) Write the difference between analog signal and digital signal.

b) Convert the following numbers.
(17E.F6)16 = (?)2
(110010100011.10100101)2 =(?)2

c) Conert the given
(125.50)10 = (?)2
(110001)2 = (?)10

d) Find

i) The Gray code equivalent of Decimal (13)

ii) Binary equivalent of Gray code 1111

iii) Hexadecimal equivalent of oct (765)

iv) Octal equivalent of Binary(11001111101011

v) Decimal avalent of binary 1010101010.

e) Write a short note on Error collection and detection code.

f) i Perform the addition of following Binary number
(1100010+1010001)
ii Perform the Subtraction of the following Binary number 1’s complement method
(11011 +10001).

 

Q. 2 Attemet any three of the following. (15M)

a) For the logic expression Y=AB+A’B’ Obtain the truth table, name the operation performed realize the operation using AND, OR NOT gate.
Also, realize it using NAND only

b) Draw the output wave format AND gate and explain it’s operation Also, discuss about 4 input AND gate.

c) Prove the following Boolean law
A+A’ B + AB’ = A+B

d) Reduce the given SOP equation using K-map method and draw the circuit and NAND network
ABC+ ABC’ +ABC + A’BC .

e) Reduce the given Pos function in Marap and draw the circuit diagram using NOR network.

 f) Using. Don’t care condition to reduced op equation and grow the circuit diagram using basic gate.
F ( P,Q,s) = ∑ (1,2,3,6,12,14 )+d (0,11,13)

 

Q. 3 Attempt any three of the following. (15M)

a) Design the Half adder using k-man. Draw the circuit diagram for the same

b) With the help of the circuit diagram discuss four-bit binary adder-subtractor.

c) Design two-bit magnitude comparator.

d) Write a short note on BCD to EXCESS-3 code converter.

e) What is Multiplier?  Draw diagram and explain4×4 bit multiplier. 

f)  Explain Full Adder in detail.

 

Q. 4 Attempting three of the following: (15M)

a) Draw the logic diagram of 4to 1 multiplexer. Explore its working.

b) Write a short note on demultiplexer.

c) Define cascading Design 16 to 1 multiplexer using 8 to 1 multiplexer

d) With the help of a diagram explain Blistable Muluvibrator.

e) What is meant by the around problem? Explain master-slave flop.

f) How J-K flip flop can used to form D  flip-flip.

 

Q. 5 Attempt any three of the following. (15M)

a) Write a short note on modulus of counter.

b) Explain the working of four-bit UP/DOWN counter.

c) Determine the number of flip-flops in mood 10 ring counter and Jonson counter. Write count Sequence in both the case d.

 d) Briefly describe the architecture of SISO shift register.

e) Explain  the design procedure for MOD 8 Binary counter.

f) The table gives below the excitation of flip-flop having inputs X1and X2. Draw the circuit excitation table of Mod 5-synchronous counter using this flip-flop for the counter sequence 000.001,010,011,100,000 Design the counter using flip-flop whose excitation tables is given below

Preset state (Qn) Next State (Qn+1) Input (X1) Input (X2)
0 0 0 0
0 1 0 1
1 0 1 x
1 1 x
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