LinkedIn Insight BSc.-Digital Electronics-Mumbai-November 2018 - Grad Plus

BSc.-Digital Electronics-Mumbai-November 2018

MUMBAI UNIVERSITY

Paper / Subject Code: 82302

Digital Electronics.

Sem : 1

Time : (2½ Hours)
[Total Marks: 75]
N. B.: (1) All questions are compulsory.
(2) Make suitable assumptions wherever necessary and state the assumptions made.
(3) Answers to the same question must be written together.
(4) Numbers to the right indicate marks.
(5) Draw neat labeled diagrams wherever necessary.
(6) Use of Non-programmable calculators is allowed.
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Q. 1. Attempt any three of the following: (15M)

a) Convert the following.
(i) (1051.36)10 = (?)8
(ii) (F9A.D5)16 = (?)10

b) What is Hamming code? A seven bit even parity hamming code is received as 1110101.
What is the correct code?

c) Certain number system has base 7. What is the hexadecimal equivalent of the minimum
and maximum number that is expressed using the base 7 and four bits?

d) Solve the following.
(i) (111000.01)2 – (100111.00)2
(ii) (1010101)2 ÷ (11)2

e) Perform the following.
(i) (727)8 + (234)8
(ii) (2C48)16 – (9AA)16 using 1C method

f) Solve the following.
(i) Convert the following number to BCD and add them (11)10 + (9)10
(ii) Convert the following number to XS-3 and subtract them (53)10 – (28)10

Q.2. Attempt any three of the following: (15M)

a) Reduce the following using Boolean laws and theorems.
(i) ???????? ̅(???? + ????) + ????????(???? ̅ + ???? ̅ )
(ii) ???????? + ???? ̅???? ̅???? + (̅????̅̅????̅ + ????)

b) Write short notes on input bubbled AND gate and input bubbled OR gate.

c. Prove the following.
(i) ????̅???????? + ???????? ̅ ???? + ????????????̅ + ???????????? = ???????? + ???????? + ????????
(ii) (???? + ????̅????) (???? + ???? ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅) = ????̅???? ̅+ ????̅????

d) Simplify using K-map and realize it using minimum number of gates.
F(A,B,C,D,E) = Σm(0,2,5,7,13,15,18,20,21,23,28,29,31)

e) Simplify using K-map and realize it using minimum number of gates.
F(A,B,C,D) = πM(4,6,8,9,10,12,13,14) +d(0,2,5)

f) Minimize expression using Quine Mc Cluskey method.
f(W,X,Y,Z)=Σm(2,6,8,9,10,11,14,15)

Q. 3. Attempt any three of the following: (15M)

a) The input to a combinational logic circuit is a 4–bit binary number. Design the logic circuit with minimum hardware for the following
(i) Output Y1 = 1 if the input binary number is 5 or less than 5.
(ii) Output Y2 = 0 if the input binary number is 9 or more than 9.

b) Convert 4 bit gray to 4 bit binary. Draw the truth table, necessary k-maps, and logic
circuit.

c) Draw circuit and explain working of XS-3 adder.

d) Design the Full Subtractor using K-map. Draw the circuit diagram for the same.

e) How Booth’s algorithm speeds up the multiplication process? Explain with an example.

f) Design single bit magnitude comparator. Draw truth table, K-map, and circuit diagram for the same.

Q. 4. Attempt any three of the following: (15M)

a) Implement full adder circuit using 8:1 MUX.

b) Cascade Demultiplexer. Build 1:8 demux using 1:4 demux chips.

c) ???? = ???? + ???? + ????̅. Realize using a multiplexer.

d) Draw logic circuit diagram of D flip flop and describe with a truth table the working of it.

e) How SR flip-flop can be used to work as T flip-flop? Explain.

f) How flip-flop is used in eliminating keyboard debouncing? Explain.

Q. 5. Attempt any three of the following: (15M)

a) Design modulo 6 ripple counter.

b) Design 4 bit binary up/down counter with control input of up/down.

c) Implement synchronous counter using JK FF for state diagram shown in figure.

d) Write a short note on buffer register.

e) Explain working of SIPO register.

f) Write a short note on Johnson’s counter.

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