 Logic Design-Engineering-Mumbai University-Dec2019 - Grad Plus

# Logic Design-Engineering-Mumbai University-Dec2019

## Semester: 3

[Total Time: 3 Hours]
[Total Marks: 80 Marks]
N.B.: 1) Q.1 is compulsory
2) Attempt any three questions out of the remaining five
3) Assume suitable data if required.
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Q. 1) Solve any four out of five: (20M)

(a) Why biasing is necessary in BJT amplifier?

b)  Solve (35)10-(47)10 using two’s compliment method.

c)  Define :

1) truth table

2) standard SOP

3) De-Morgan’s theorem

4) Duality theorem

5) universal gate

d)  Define multiplexer and state its application.

e)  Convert S-R flip-flop to T flip-flop.

Q. 2) a) Using Quine-Me-dusky method determine minimum SOP form for f(A, B, C, D)=∑m(0,1,3,7,8,9,11,15). (10M)

b) What do you mean by differential amplifier? What is its primary function? State different configuration of it, which one is popularly used. (10M)

Q. 3) Draw & explain Ring counter using suitable waveforms. (10M)

b)Implement the following using only one 4:1 MUX and few gates: (10M)

f(A, B, C, D)=∑m(0,1,3,4,5,7,9,10,12,15)

Q. 4) a) Design MOD-9 Synchronous counter using J-K flip-flop.(10M)

b) Design four bit BCD adder using IC7483. (10M)

Q. 5) a) What is shift register? Mention different modes of operation of shift register?

b) State and explain various VHDL data objects in brief. (10M)

Q. 6) Solve the following (Any Four). (20M)

a) VHDL program format.

b) Difference between combinational circuit and sequential circuits.

c) Different biasing methods.

d) Race-around condition in flip-flop.

e) Current mirror circuit.

f) Arithmetic logic unit.

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