LinkedIn Insight Summer 2016 - Q.3 - Grad Plus

Summer 2016 – Q.3

3. (a) Draw a neat diagram of 3-input inverting summing amplifier and obtain expression for its sip voltage. [6M]

In this simple summing amplifier circuit, the output voltage, ( Vout ) now becomes proportional to the sum of the input voltages, V1, V2, V3, etc.

$latex \begin{array}{l}I_F=I_1+I_2+I_3=-\left[\frac{V_1}{R_{in}}+\frac{V_2}{R_{in}}+\frac{V_3}{R_{in}}\right]\\\\Inverting\;Equation:\;V_{out}=-\frac{R_f}{R_{in}}\times V_{in}\\\\\therefore-V_{out}=\left[\frac{R_F}{R_{in}}V_1+\frac{R_F}{R_{in}}V_2+\frac{R_F}{R_{in}}V_3\right]\end{array}$

However, if all the input impedances, ( Rin ) are equal in value, we can simplify the above equation to give an output voltage of: Summing Amplifier Equation

$latex V_{out}=-\frac{R_F}{R_{IN}}\left(V_1+V_2+V_3……etc\right)$

(b) Compare synchronous and asynchronous counter. [4M]
Sr. No. Parameter Asynchronous counter synchronous counter
1. Circuit complexity Logic circuit simple. With increase in number of states, thee logic circuit becomes complicated.
2. Connection pattern Output of thee preceding FF, is connected to clock of the next FF. There is no connection between output of preceding FF and CLK of next one.
3. Clock input All the FFs are not clocked simultaneously. All FFs receive clock signal simultaneously.
4. Propagation delay P.D.=n×(td) where n is number of FF and td is p.d. per FF. P.D.=n×(td)FF+(td)gate. It is much shorter than that of asynchronous counter.
5. Maximum frequency of operation Low because of the long propagation delay. High due to shorter propagation delay.

(c) State Demorgan’s theorem. [2M]

De-Morgan’s First Theorem
According to De-Morgan’s first theorem, a NOR gate is equivalent to a bubbled AND gate.

$latex \begin{array}{l}Z=\overline{A+B}\\\end{array}$

For the bubbled AND gate the equation is

$latex \begin{array}{l}Z=\overline{A\cdot B}\\\end{array}$

De-Morgan’s Second Theorem
De-Morgan’s Second Theorem states that the NAND gate is equivalent to a bubbled OR gate.
The Boolean expression for the NAND gate is given by the equation shown below.

$latex \begin{array}{l}Z=\overline{A\cdot B}\\\end{array}$

The Boolean expression for the bubbled OR gate is given by the equation shown below.

$latex \begin{array}{l}Z=\overline{A+B}\\\end{array}$

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