Summer 2018- Q.1 solution

Solution:- Figure shows the internal architecture of 8086. The 8086 microprocessor is divided into two functional parts.
1) Bus Interface Unit (BIU)
2) Execution Unit (EU)

Bus Interface Unit (BIU):- BIU performs all the activity related to “Bus”. It performs following operations:-

(i) It sends out address.

(ii) It fetches instruction from memory.

(iii) Reads data from ports and memory.

(iv) Writes data to ports and memory.

Thus all transfers of data and addresses required for execution unit is handled by BIU. BIU has following components:

(1) Segment Register

(2) Instruction Pointer

(3) Address generation adder,

4) Queue

5) Bus control logic.

1) Segment Register:- The BIU consist of following four segment register.

i) Code segment (CS).

ii) Stack segment (SS)

iii) Data Segment (DS).

IV) Exrtra segment(ES).

All these segment registers are used to hold the upper 16 bits starting address of four memory segment. The 8086 BIU sends out 20-bit addresses, So, it can address of 2²⁰ or 1048576 bytes in memory.

2) Instruction Pointer:- Code segment register holds the upper 16 bits of the starting address of the segment from which BIU is currently fetching instruction code bytes. The IP register holds the 16 bit address, normally referred as offset, of the next code byte within the current code segment. The instruction pointer is updated by the BIU, so that it contain the offset of the next instruction from the beginning of the current code segment i.e. IP points to the next instruction, CS &IP continuosly produces 20 bit physical address from where BIU fetches instruction code bytes.

3)Address generation adder:- As the name suggest this block is a adder block for generating address. In 8086 directly physical address is not generated. It is combination of segment register & offset. Secondly addition is also not direct. firstly segment register is shifted four bits left & then offset is added.

4) Queue:- To speed microprocessor program execution, the BIU fetches as many as six instruction bytes ahead of time from memory. The prefetched instruction bytes are held for the EU in a first-in-first-out (FIFO) group of register called queue.

5) Bus Control Logic:- BIU handles all the activities related to bus, it means that read/write data to memory I/O, fetching instruction from memory, sending out adress, all these activities are performed by it. therefore it has to generate following signals.

i) Address line signals

ii) Data bus signals

iii) Read signals

iv) Write signals

v) Memory or IO operation

vi) ALE signal

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