Question 36: For the given circuit, the input digital signals are applied at the terminals \mathrm{A}, \mathrm{B} and C. What would be the output at the terminal y ?
(1) Output waveform as shown in option (1)
(2) Output waveform as shown in option (2)
(3) Output waveform as shown in option (3)
(4) Output waveform as shown in option (4)
Answer: Option (3)
Explanation:
From the given logic circuit, the upper gate is an AND gate taking inputs \mathrm{A} and \mathrm{B}. Hence its output is \mathrm{A}\cdot \mathrm{B}.
The lower gate is an AND gate with an inversion bubble at the output, which makes it a NAND gate.
Its inputs are \mathrm{B} and \mathrm{C},
so its output is \overline{\mathrm{B}\cdot \mathrm{C}}.
The outputs of these two gates are applied to an OR gate. Therefore, the final output is given by
\mathrm{y} = \mathrm{A}\cdot \mathrm{B} + \overline{\mathrm{B}\cdot \mathrm{C}}Using De Morgan’s theorem, \overline{\mathrm{B}\cdot \mathrm{C}} = \overline{\mathrm{B}} + \overline{\mathrm{C}}. Thus,
\mathrm{y} = \mathrm{A}\cdot \mathrm{B} + \overline{\mathrm{B}} + \overline{\mathrm{C}}From the given timing diagrams of \mathrm{A}, \mathrm{B},
and \mathrm{C}, the term \overline{\mathrm{B}} + \overline{\mathrm{C}} remains high for most intervals except when both
\mathrm{B} and \mathrm{C} are simultaneously high.
Evaluating the expression \mathrm{y} = \mathrm{A}\cdot \mathrm{B} + \overline{\mathrm{B}\cdot \mathrm{C}} over the time intervals \mathrm{t}_1 to \mathrm{t}_6, the output waveform matches exactly with the waveform shown in option (3).
Hence, the correct output at terminal \mathrm{y} is given by option (3).