Analysis of GATE EC Previous Papers for Subject Digital Circuits

Aspiring engineers who are preparing for the Graduate Aptitude Test in Engineering (GATE) understand the significance of thorough preparation and comprehensive study resources.

Through a meticulous examination of previous years’ question papers, we aim to provide you with valuable insights, key trends, and effective strategies to excel in Digital Circuits for your GATE exam.

GATE EC Syllabus for the Subject Digital Circuits

Number Representations: binary, integer and floating-point- numbers.

Combinatorial circuits: Boolean algebra, minimization of functions using Boolean identities and Karnaugh map, logic gates and their static CMOS implementations, arithmetic circuits, code converters, multiplexers, decoders.

Sequential Circuits: latches and flip-flops, counters, shift-registers, finite state machines, propagation delay, setup and hold time, critical path delay.

Data Converters: sample and hold circuits, ADCs and DACs.

Semiconductor Memories: ROM, SRAM, DRAM.

Computer Organization: Machine instructions and addressing modes, ALU, data-path and control unit, instruction pipelining.

Analysis of Previous GATE Papers for Digital Circuits

Recent GATE Paper Questions of Digital Circuits

The following questions have been asked from Digital Circuits , in GATE-EC 2023 Paper.

Q.1. For the circuit shown below, the propagation delay of each NAND gate is 1 ns. The critical path delay, in ns, is __ (rounded off to the nearest integer).

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Q.2. In the circuit shown below, P and Q are the inputs. The logical function realized by the circuit shown below is

a) Y= PQ

b) Y=P+Q

c) Y= \overline{PQ}

d) Y= \overline{P+Q}

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Q.3. The synchronous sequential circuit shown below works at a clock frequency of 1 GHz. The throughput, in Mbits/s, and the latency, in ns, respectively, are

a) 1000, 3

b) 333.33, 1

c) 2000, 3

d) 333.33, 3

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